1. Field of the Invention
This invention relates to a Hall IC (integrated circuit) using a GaAs substrate.
2. Description of the Related Art
Two types of monolithic Hall ICs using a GaAs substrate are known. The first type incorporates a Hall element and an amplifier for amplifying the output of the Hall element. The second type is identical to the first type, except that it further incorporates a Schmitt circuit (or the like) for subjecting the output of such an amplifier to A/D (analog-to-digital) conversion. The second type is disclosed by, for example, Published Unexamined Japanese Patent Application No. 62-113016, published May 23, 1987.
If the GaAs substrate is diced with a blade in the forward mesa direction, chipping of the substrate and/or zigzag cutting thereof will easily occur. Here, the forward mesa direction corresponds to the direction of a crystal axis &lt;011&gt;. If the GaAs substrate is etched or diced in the forward mesa direction in the cleavage plane, the cross section of the crystal structure shows a trapezoid having an upside and a base longer than the upside. On the other hand, the reverse mesa direction corresponds to the direction of a crystal axis &lt;011&gt;. If the substrate is etched or diced in the reverse mesa direction in the cleavage plane, the cross section of the crystal structure shows a reverse trapezoid having an upside and a base shorter than the upside. To avoid chipping or zigzag cutting, to make the required area of a pellet smaller, the pellet is usually diced at an angle of .+-.45.degree. to the cleavage direction. Further, to enhance the intensity of integration, FETs (Field Effect Transistors) and resistors have current paths extending in parallel with dicing lines formed in the substrate, that is, extending at an angle of .+-.45.degree. to the cleavage direction.
However, in the above-described conventional art, it is difficult to enhance the conductance (gm) of amplifying FETs, serving as a part of the amplifier, for receiving the output of the Hall element. This is because of the following:
The conductance (gm) is increased by shortening the gate length of a FET. However, if the FET has a current path extending in the direction of a crystal axis &lt;010&gt; or &lt;001&gt;, the conductance reaches a maximum value when the gate length is about 2 .mu.m. Thus, the gain of the amplifier and hence the output voltage thereof cannot be further increased. Also the minimum magnetic force the device can detect cannot be further lowered. More specifically, if the magnetic field intensity is 1K gauss, and the output voltage of the Hall element (sensor) is 100 mV, the gain of the amplifier is about 10, and therefore the output voltage of the amplifier is only about 1 V only. This may cause erroneous operational of an operation amplifier, if it is connected to the output terminal of the amplifier. Alternatively, if an A/D converter is connected to the output terminal of the amplifier, the minimum magnetic force the device can detect is as large as about 300 gauss. That is, the device cannot detect a magnetic field of low intensity.